1. Field of the Invention
This invention relates to shifters and more particularly to a method and circuit for sign fill shifting of operands.
2. Description of the Relevant Art
Microprocessors determine the speed and power of personal computers, and a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input output unit (I/O unit), the control unit, and the arithmetic-logic unit (ALU). The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of a signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the program is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor.
Division is an important computation to be performed by any ALU. Division in binary mathematics is accomplished by shifting right the operand to be divided by a shift count equal to the divisor. For example, dividing an operand by four is accomplished by shifting the operand right by two bits. Division can be performed on signed or unsigned operands. For signed operands the most significant bit is typically the sign bit. With respect to unsigned operands, division is performed by shifting with zero fill. With respect to signed operands, division is accomplished by shifting with signed fill.
A frequent logical operation to be performed by ALUs is the "shift arithmetic right" instruction which is part of the x86 instruction set. The shift arithmetic right instruction in essence causes a signed operand to be right shifted with sign fill. Shift arithmetic right, in essence, equates to division with sign fill.
FIG. 1 is a block diagram of relevant portions of an ALU of the prior art including a shift arithmetic right (SAR) circuit 10 for executing shift arithmetic right or sign division instructions. SAR 10 includes a fan out circuit 12 coupled to a right double shifter 14.
Right double shifter 14 includes a set of lower inputs (not shown) configured to receive a multiple bit operand (a.sub.n:1), subject to a shift arithmetic right instruction or a signed division operation, and a second set of upper inputs (not shown) coupled to the output of the fan out circuit 12.
Fan out circuit 12 includes an input node configured to receive the most significant bit (i.e., the sign bit) of a.sub.n:1. Fanout circuit is coupled to a control node 18 which receives an enable signal from the control unit (not shown). In response to fan out circuit 12 receiving the enable signal, fan out circuit 12 operates to produce an m bit operand (e.sub.m:1) each bit of which equates to the sign bit of the input operand a.sub.n:1. The m bit operand of the fan out circuit 12 is provided to the upper input nodes of the right double shifter 14 concurrently with the input operand a.sub.n:1 to be shifted.
Right double shifter 14 is coupled to shift count input node(s) 22. In response to receiving the m bit sign operand e.sub.m:1, a.sub.n:1, and a shift count at shift count input node(s) 22, right double shifter 14 operates to generate an n bit result operand r.sub.n:1 representing the input operand a.sub.n:1 right shifted by the shift count and sign filled. The combination of fan out circuit 12 and right double shifter 14 operates to execute shift arithmetic right instructions or operand division instructions.
One of ordinary skill in the art will recognize that fan out circuit 12 introduces signal delay to the critical path of the ALU containing the SAR 10. For any shift arithmetic right operation, operation of double right shifter 14 must be delayed until arrival of the m bit operand e.sub.m:1 from fan out circuit 12. This delay may require SAR circuit 10 to operate in more than one clock cycle. Moreover, one of ordinary skill in the art will recognize that fan out circuit 12 must be able to provide the upper input nodes of right double shifter 14 with m bit operands e.sub.m:1 of multiple size in order to accommodate sign fill shifting of input operands of multiple size. The ability of fan out circuit 12 to provide double right shifter 14 with multiple sized operands e.sub.m:1 requires fan out circuit 12 to be complex and capable of operating in several modes according to differing enable signals.